1. Field of the Invention
The present invention relates to a sampling circuit and the associated sampling method, especially to a sampling circuit and the associated sampling method that improves a sampling accuracy and reduces a slew time of a sampling signal.
2. Description of Related Art
FIG. 1 illustrate a circuit of a conventional bootstrapped switch, which is a common switching and sampling circuit. A reference “Input switch configuration suitable for rail-to-rail operation of switched opamp circuits” from IEE Electronics Letters (1999 January, pp. 8-9) has conducted a research on this circuit. The bootstrapped switch 100 includes switches 110, 120, 130, 140 and 150, an NMOS 160 and a capacitor 170. An input, a node receiving the input voltage VI, and an output, a node outputting the output voltage VO, of the bootstrapped switch 100 are respectively coupled to a source and a drain of the NMOS 160. A gate of the NMOS 160 is coupled to a voltage source V3 through the switch 150 as well as coupled to the capacitor 170 and one terminal of the switch 110 through the switch 140. The other terminal of the switch 110 is coupled to a voltage source V1. The other terminal of the capacitor 170 is coupled to a voltage source V2 through the switch 120 as well as coupled to the source of the NMOS 160 and the input of the bootstrapped switch 100 through the switch 130. The voltage source V1 is of a high voltage level VDD while the voltage sources V2 and V3 are coupled to the ground. Basically, the operation of the bootstrapped switch 100 can be divided into two phases. In the first phase when the switch 110, the switch 120 and the switch 150 switch on while the switch 130 and the switch 140 switch off, the capacitor 170 is gradually charged to VDD and the NMOS 160 is off because the gate thereof is coupled to the ground. In the second phase when the switch 110, the switch 120 and the switch 150 switch off while the switch 130 and the switch 140 switch on, a gate voltage of the NMOS 160 is equal to the input voltage VI plus a voltage drop across the capacitor 170. A formula of an on resistance Ron of a MOM-ET can be expressed as:
                              R          on                =                  1                                    (                                                V                  GS                                -                                  V                  th                                            )                        ⁢                          μ              n                        ⁢                          C              OX                        ⁢                          W              L                                                          (        1        )            Thus, the on resistance Ron of the NMOS 160 in the second phase can be expressed as:
                              R          on                =                              1                                          (                                  VDD                  +                  VI                  -                  VI                  -                                      V                    th                                                  )                            ⁢                              μ                n                            ⁢                              C                OX                            ⁢                              W                L                                              =                      1                                          (                                  VDD                  -                                      V                    th                                                  )                            ⁢                              μ                n                            ⁢                              C                OX                            ⁢                              W                L                                                                        (        2        )            Notice that the on resistance Ron does not vary with the input voltage VI, and therefore a sampling linearity of the bootstrapped switch 100 can be improved.
The on resistance of the NMOS 160 is independent of the input voltage VI because the conventional bootstrapped switch 100 makes the gate voltage of the NMOS 160 in an on state related to the input voltage VI by having the capacitor 170 coupled between the gate and the source of the NMOS 160 and pre-charged to VDD before the NMOS 160 is turned on by the gate voltage VDD. Unfortunately, the capacitor 170 also increases a capacitive load of the bootstrapped switch 100. It is even worse that when multiple bootstrapped switches 100 are connected in parallel in a multi-bit application circuit, a front-stage circuit thereof encounters even greater capacitive load, which influences stability of an output voltage of the front-stage (i.e., the input voltage VI of the bootstrapped switch 100), resulting in, for example, a degraded phase margin or a reduced bandwidth, which in turn influences a sampling accuracy of the bootstrapped switch 100. Moreover, the increased capacitive load also causes a slew time required by the sampling signal of the bootstrapped switch 100 to increase, degrading the sampling linearity of the bootstrapped switch 100.